Differential Equations and Control Processes
(Differencialnie Uravnenia i Protsesy Upravlenia)

Lock-in range of classical PLL with piecewise-linear phase detector characteristic

Author(s):

Nikolay Vladimirovich Kuznetsov

Department of Applied Cybernetics,
Saint Petersburg State University, 199034, Saint Petersburg, Russia
Institute of Problems in Mechanical Engineering,
Russian Academy of Sciences, 199178, Saint Petersburg, Russia

nkuznetsov239@gmail.com

Mikhail Valeryevich Blagov

Department of Applied Cybernetics,
Saint Petersburg State University, 199034, Saint Petersburg, Russia

mikhail.blagov@gmail.com

Konstantin Dmitrievich Alexandrov

Department of Applied Cybernetics,
Saint Petersburg State University, 199034, Saint Petersburg, Russia

Marat Vladimirovich Yuldashev

Department of Applied Cybernetics,
Saint Petersburg State University, 199034, Saint Petersburg, Russia

Renat Vladimirovich Yuldashev

Department of Applied Cybernetics,
Saint Petersburg State University, 199034, Saint Petersburg, Russia

Abstract:

Phase-locked loops (PLL) are classical nonlinear control systems that are used to tune frequency and phase in electrical circuits. In this article a problem of the lock-in range estimation for classical PLLs with piecewise-linear phase detector characteristic and first-order filters is studied. A new analytical-numerical method of the lock-in range estimation is discussed. Estimations obtained using this method are compared with previously known ones.

Keywords

• lock-in range
• nonlinear analysis
• Phase-locked loops
• PLL

References:

1. Viterbi A. Principles of coherent communications. New York: McGraw-Hill, 1966. P. 321
2. Leonov G. A. Phase-locked loops. Theory and application // Automation and Remote Control. 2006. Vol. 10. P. 1573-1609
3. Shalfeev V. D., Matrosov V. V. Nonlinear dynamics of phase synchronization systems (in Russian). Nizhni Novgorod University Press, 2013
4. Shakhtarin B. I., Sizykh V. V., Sidorkina Yu. A. Sinkhronizatsiya v radiosvyazi i radionavigatsii [Synchronization in radio communication and navigation] // Moscow, Goryachaya Liniya-Telekom Publ. 2011
5. Best R. E. Phase-Locked Loops: Design, Simulation and Application. 6th edition. McGraw-Hill, 2007. P. 490
6. Kolumban G. Software Defined Electronics: A Revolutionary Change in De- sign and Teaching Paradigm of RF Radio Communications Systems // ICT Express. 2015. Vol. 1, no. 1. P. 44 - 54
7. Best R. E. Costas Loops: Theory, Design, and Simulation. Springer International Publishing, 2018
8. Ladvanszky J. A Costas loop variant for large noise // Journal of Asian Scientific Research. 2018. Vol. 8, no. 3. P. 144 - 151
9. Alexandrov K. D., Kuznetsov N. V., Leonov G. A. et al. Pull-in range of the classical PLL with impulse signals // IFAC-PapersOnLine. 2015. Vol. 48, no. 1. P. 562-567
10. Best R. E. Phase-locked Loops: Design, Simulation, and Applications. Mc- Graw Hill, 1984
11. Kihara M., Ono S., Eskelinen P. Digital Clocks for Synchronization and Communications. Artech House, 2002. P. 269
12. Abramovitch D. Phase-Locked Loops: A control Centric Tutorial // American Control Conf. Proc. Vol. 1. IEEE, 2002. P. 1-15
13. De Muer B., Steyaert M. CMOS Fractional-N Synthesizers: Design for High Spectral Purity and Monolithic Integration. Springer, 2003
14. Dyer S. A. Wiley Survey of Instrumentation and Measurement. Wiley, 2004
15. Shu K., Sanchez-Sinencio E. CMOS PLL synthesizers: analysis and design. Springer, 2005
16. Goldman S. J. Phase-Locked Loops Engineering Handbook for Integrated Circuits. Artech House, 2007
17. Egan W. F. Phase-Lock Basics. Wiley-IEEE Press, 2007
18. Baker R. J. CMOS: Circuit Design, Layout, and Simulation. IEEE Press Series on Microelectronic Systems. Wiley-IEEE Press, 2011
19. Ndjountche T. CMOS Analog Integrated Circuits: High-Speed and Power- Efficient Design. CRC Press, 2017
20. Kroupa V. F. Frequency Stability: Introduction and Applications. IEEE Series on Digital & Mobile Communication. Wiley-IEEE Press, 2012. P. 328
21. Rouphael T. J. Wireless Receiver Architectures and Design: Antennas, RF, Synthesizers, Mixed Signal, and Digital Signal Processing. Elsevier Science, 2014
22. Purkayastha B. B., Sarma K. K. A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel. Springer, 2015
23. Middlestead R. W. Digital Communications with Emphasis on Data Modems: Theory, Analysis, Design, Simulation, Testing, and Applications. Wiley, 2017
24. Aleksandrov K. D., Kuznetsov N. V., Leonov G. A. et al. Lock-in range of classical PLL with impulse signals and proportionally-integrating filter // arXiv preprint arXiv:1603. 09363. 2016
25. Leonov G. A., Kuznetsov N. V., Yuldashev M. V., Yuldashev R. V. Hold-in, pull-in, and lock-in ranges of PLL circuits: rigorous mathematical definitions and limitations of classical theory // IEEE Transactions on Circuits and Systems_I: Regular Papers. 2015. Vol. 62, no. 10. P. 2454-2464
26. Kuznetsov N. V. Analytical-numerical methods for the study of hidden oscillations (Habilitation thesis, in Russian). Saint-Petersburg State University, 2016
27. Aleksandrov K. D., Kuznetsov N. V., Leonov G. A. et al. Lock-in range of classical PLL with impulse signals and proportionally-integrating filter // arXiv preprint arXiv:1603. 09363. 2016
28. Gardner F. M. Phaselock techniques. New York: John Wiley & Sons, 1966. P. 182
29. Shakhgil'dyan V. V., Lyakhovkin A. A. Fazovaya avtopodstroika chastoty (in Russian). Moscow: Svyaz', 1966
30. Leonov G. A., Kuznetsov N. V., Yuldashev M. V., Yuldashev R. V. Analytical method for computation of phase-detector characteristic // IEEE Transactions on Circuits and Systems - II: Express Briefs. 2012. Vol. 59, no. 10. P. 633_647
31. Ladvanszky J. A Costas loop with di? erential coding // IJCRR. 2017. P. 20305- 20310
32. Kuznetsov N. V., Kuznetsova O. A., Leonov G. A. et al. Simulation of nonlinear models of QPSK Costas loop in MatLab Simulink // 2014 6th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT). Vol. 2015-January. IEEE, 2014. P. 66-71
33. Leonov G. A., Aleksandrov K. D. Frequency-Domain Criteria for the Global Stability of Phase Synchronization Systems // Doklady Mathematics. 2015. Vol. 92, no. 3. P. 764-768
34. Alexandrov K. D., Kuznetsov N. V., Leonov G. A. et al. Pull-in range of the PLL-based circuits with proportionally-integrating filter // IFACPapersOnLine. 2015. Vol. 48, no. 11. P. 720-724
35. Best R. E., Kuznetsov N. V., Leonov G. A. et al. Tutorial on dynamic analysis of the Costas loop // IFAC Annual Reviews in Control. 2016. Vol. 42. P. 27-49
36. Huque A. S., Stensby J. L. An exact formula for the pull-out frequency of a 2nd-order type II phase lock loop // IEEE Communications Letters. 2011
37. Vol. 15, no. 12. P. 1384 - 1387. Shakhtarin B. I. Study of a piecewise-linear system of phase-locked frequency control // Radiotechnica and electronika (in Russian). 1969. no. 8. P. 1415-1424
38. Blagov M. V. Analytical-numerical methods of lock-in range estimation for two-dimensional PLL (thesis) (scientific supervisor - N. V. Kuznetsov). (in preparation), 2019

Full text (pdf)